Concurrent Error Detection in Digit-Serial Normal Basis Multiplication over GF(2m)
Chiou‐Yng Lee · 2008
Parity prediction schemes have been widely studied in the past. Recently, it has been demonstrated that this prediction scheme can achieve fault-secureness in arithmetic circuits for stuck-at and stuck-open faults. For most cryptographic applications, encryption/decryption algorithms rely on computations in very large finite fields. The hardware implementation may require millions of logic gates and this may lead to the generation of erroneous outputs by the multiplier. In this paper, a concurrent error detection (CED) technique is used in the digit-serial basis multiplier over finite fields of characteristic two. It is shown that all types of normal basis multipliers possess the same parity prediction function.