Architecture for single-chip ASIC processor with integrated floating point unit
Vojin G. Oklobdzija · 1988
An architecture for a single-chip processor with emphasis on ASIC (application-specific integrated-circuit) implementation is presented. The basic principles of RISC architecture are applied to the processor, and fast floating-point and serial I/O units are included on the chip. The limitation of the processor's complexity is the 50000-gate capacity of the chip and 600-pS-per-gate delay. These are the characteristics of vendor CMOS-ASIC technology currently available. The architecture is a tradeoff between the features desirable to make the processor attractive for a wide range of computational problems and the possibilities of the available technology. It takes advantage of the high level of integration and low power consumption that is achievable with CMOS technology. It also benefits from the elimination of clock skews and off-chip delay penalties associated with comparable implementations using several chips.>