A CMOS 50% duty cycle repeater using complementary phase blending
Kazuyuki Nakamura, Muneo Fukaishi, Y. Hirota, Y. Nakazawa, Michio Yotsuyanagi · 2002
The authors report a duty cycle repeater (DCR) which obtains 50% duty-cycle complementary clock signals from a wide range of input duty-cycle signals from 30% to 70%, even when input signals suffer from timing skew. It features a simple CMOS structure, with a newly developed complementary phase blending architecture and a symmetrical phase blending inverter.