A new decimal antilogarithmic converter
Dongdong Chen, Yu Zhang, Daniel Teng, Khan A. Wahid, Moon Ho Lee, Seok‐Bum Ko · 2009
This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) antilogarithmic converter based on the digit-recurrence algorithm with selection by rounding. The converter can calculate the accurate antilogarithm (10dec) of the 32-bit DFP numbers which are defined in the IEEE 754-2008 standard. The sequential architecture of the proposed 32-bit DFP antilogarithmic converter is implemented on Xilinx Virtex-II Pro P30 FPGA device. The proposed architecture occupies 2, 315 out of 13696(16%) slices and can obtain a faithful 32-bit DFP antilogarithm in 11 clock cycles running at 51.5 MHz. The 7-digit decimal fixed-point (FXP) antilogarithmic converter is an essential operational part of the 32-bit DFP antilogarithmic converter. We transform it to a 7-digit decimal exponential converter to compare with a 24-bit binary FXP exponential converter. The compared results show that the 7-digit decimal exponential converter occupies 2.18 times more area and 1.66 times slower than the 24-bit binary FXP exponential converter.