Parallelism in mainstream enterprise platforms of the future
Dileep Bhandarkar · International Conference on Parallel Architectures and Compilation Techniques · 2002
Today’s leading edge microprocessors feature over 200 million transistors. Moore’s Law continues to provide a doubling of the transistor density every two years. This has spawned several new changes in the features designed into commercially available microprocessors. Intel’s Itanium Processor Family features massive on-chip execution resources as evidenced by the 6 integer units, 3 branch units, 2 floating point multiply-add units, and 2 load and 2 store units in the recently released Itanium 2 processor. Intel’s Xeon processor introduced simultaneous multi-threading (SMT) in a high volume microprocessor. IBM’s Power4 * microprocessor represents the first “SMP-on-a-chip” design for high-end enterprise servers—two processors with Level 2 (L2) cache are incorporated on each chip. Future microprocessors will offer higher levels of multiprocessor capability on chip as the transistor density increases. Computer manufacturers are incorporating these high-end microprocessors into large symmetric multiprocessing systems with 8, 16, 32 or even 64 processors. Another trend is the emergence of clustered commercially off the shelf (COTS) servers as credible supercomputing platforms. These trends provide compiler writers and application developers a wide range of platforms for developing parallel applications ranging from instruction level parallelism (ILP) in high-end microprocessors, to tightly coupled thread level parallelism (TLP) and massive message oriented parallelism in large-scale clusters. This talk will cover anticipated advances in semiconductor technology and relate those to trends in microprocessor design that will drive higher levels of parallelism in mainstream server platforms.