Synthesis of ladder diagrams from Petri nets controller models
Ismael Jiménez, Edgar Fernando García López, Antonio Ramírez‐Treviño · 2002
This paper addresses the problem of automated synthesis of ladder diagrams for programmable logic controllers (PLC). The programs are obtained from control specifications expressed as timed interpreted Petri nets (TIPN). The approach herein presented allows to rapidly synthesize correct programs for PLC; it is based on a set of simple translation rules that produces a ladder diagram (LD) from a TIPN. Moreover this set of rules was coded into a program to automate this process.