Exploiting Spatial and Temporal Parallelism in the Multithreaded Node Architecture Implemented on Superscalar RISC Processors
Dae-Joon Hwang, SangLyul Cho, Y. D. Kim, S. Y. Han · 1993
In most multithreaded node architectures moti- vated by the dataflow computational model, spatial parallelism could not be exploited at the thread level due to the resource deficit incurred by their inter nal organization. So we proposed a node architecture exploiting both spatial and temporal parallelism of a program. A multi-port non-blocking data cache is in corporated into our design to cope with the excessive data bandwidth required in parallel execution of mul tiple threads. The proposed node architecture may contribute to greatly reducing communication latency through the interconnection network. Simulation re sults show that parallel loops can be executed on this architecture more efficiently than on other competi tive ones.