Design of low-cost and high-throughput linear arrays for DFT computations: algorithms, architectures, and implementations
Wei-Ren Shiue, Shen‐Fu Hsiao · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2000
Recursive algorithms for discrete Fourier transform (DFT) computation are proposed, where the common entries of the decomposed matrices are factored out in order to reduce the number of multipliers during implementation. The derived algorithms are essentially band-matrix-vector multiplications with matrix bandwidth of 3 in the radix-2 case and bandwidth of 7 in the radix-4 case. Low cost architectures are derived using an efficient mapping technique for the corresponding heterogeneous dependence graphs of the decomposed band matrices. Only log/sub 2/ N(3 log/sub 4/ N) adders and log/sub 2/ N-1(log/sub 4/ N-1) multipliers are needed to compute the DFT of size N using the proposed radix-2 (radix-4) linear array architectures, a great saving in hardware cost compared to previous approaches. Due to the simplicity and regularity of the architectures, it is possible to reduce the power consumption of the DFT processors by temporarily disabling the multiplier units at proper time steps. VLSI implementations of an 8-point radix-2 DFT processor and a 64-point radix-4 DFT processor are also given.