Energy-Efficient Multi-Pipeline Architecture for Terabit Packet Classification
Weirong Jiang, Viktor K. Prasanna · 2009
Energy efficiency has become a critical concern in designing high speed packet classification engines for next generation routers. Although TCAM-based solutions can provide high throughput, they are not scalable with respect to power consumption. On the other hand, mapping decision-tree-based packet classification algorithms onto SRAM-based pipeline architectures becomes a promising alternative to TCAMs. However, existing SRAM-based algorithmic solutions need a variable number of accesses to large memories to classify a packet, and thus suffer from high energy dissipation in the worst case. This paper proposes a partitioning-based multi-pipeline architecture for energy-efficient packet classification. We optimize the HyperCuts algorithm, which is considered among the most scalable packet classification algorithms, and build a decision tree with a bounded height. Then we study two different schemes to partition the decision tree into several disjoint subtrees and map them onto multiple SRAM-based pipelines. Only one pipeline is active for classifying each packet, which takes a bounded number of accesses to small memories. Thus the energy dissipation is reduced. Simulation experiments using both real-life and synthetic traces show that the proposed architecture with 8 pipelines can store up to 10 K unique rules in 0.336 MB SRAM, sustains 1 Tbps throughput, and achieves 2.25-fold reduction in energy dissipation over the baseline pipeline architecture that is not partitioned.