Design and implementation of a scalable encryption processor with embedded variable DC/DC converter
James Goodman, Anantha P. Chandrakasan, A.P. Dancy · 1999
This work describes the design and implementation of an energy-efficient, scalable encryption processor that utilizes variable voltage supply techniques and a highefficiency embedded variable output DC/DC converter.The resulting implementation dissipates 134nJ/bit @ V DD = 2.5V, when encrypting at its maximum rate of 1Mb/s using a maximum datapath width of 512 bits.The embedded converter achieves an efficiency of 96% at this peak load.The processor is 2-3 orders of magnitude more energy efficient than optimized assembly code running on a low-power processor such as the StrongARM.