Parallelized radix-2 scalable Montgomery multiplier
Nan Jiang, David Money Harris · 2007
This paper describes the FPGA implementation of a parallelized scalable radix-2 Montgomery multiplier. It improves upon previous designs by rearranging previously sequential calculations to take place in parallel. On a Virtex-II FPGA, this design can perform 1024-bit modular exponentiation in 6.3 ms using 6006 lookup tables, a 17 % speed improvement over the previously fastest scalable radix-2 Montgomery multiplier.