Multiplierless implementation of all-pole digital filters
M. Bhattacharya, T. Saramäki · 2003
For some low sensitivity structures, the coefficient values are quite small. These values after converting them to minimum signed powers-of-two (MNSPT) or canonic signed digit (CSD) forms can be implemented in a multiplierless manner, i.e., by using only a few bit shifts and adds and/or subtracts. In such cases, the number of nonzero bits required for coefficient representations become quite low. This paper proposes a structure that is very suitable for implementing all-pole digital filters. When accepting a marginal deviation from the given specifications, the required number of nonzero bits becomes very low, making the overall implementation attractive. Alternatively, one can start with a filter that slightly exceeds the given criteria without increasing the filter order. Then, the coefficient values are quantized into the desired representation forms such that the given overall criteria are still met.