On the design of robust testable CMOS combinational logic circuits
Sandip Kumar Kundu, Sudhakar M. Reddy · 2003
The authors propose an integrated approach to the design of combinational logic circuits in which stuck-open faults and path delay faults are detectable by robust tests that detect modeled faults independent of the delays in the circuit under test. They demonstrate that the proposed designs and tests guarantee the design of CMOS logic circuits in which all path delay faults are locatable. >