Hierarchical DFT with enhancements for AC scan, test scheduling and on-chip compression - a case study
Jeff Remmers, D. Lee, Rick Fisette · 2006
The DFT architecture, pattern generation and application, and economic issues encountered in large ASIC designs are increased when at-speed testing is introduced. This case study shows enhancements over the current state of the art hierarchical methodology by improving transition testing, test scheduling, and using compression on a production design.