Constrained Test Generation for Embedded Synchronous Sequential Circuits With Serial-Input Access
Irith Pomeranz · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2004
We describe a constrained test-generation procedure for synchronous sequential circuits embedded in a large design where scan is used to provide access to the inputs of the individual circuits. The constrained test-generation procedure generates test sequences, where each vector is obtained from the previous one by shifting the scan chain a limited number of positions. Such constrained sequences can be applied through a scan chain with minimal test-application time overhead due to scan. When a shift by a single position is used to obtain each vector from the previous one, the constrained test sequences can allow functional (at-speed) testing of the circuit. Although constrained test sequences cannot achieve complete fault coverage, they reduce the overall test-application time required to achieve complete fault coverage when used together with unconstrained test sequences. We demonstrate these features through experimental results.