Post-placement buffer reoptimization
D. Brasen, Thomas J. Schaefer, A. Ginetti, Shu Han Chu · 2003
In this paper the timing of an existing placement is improved by netlist modification. Placement timing is defined as the maximum delay along the most critical path plus the maximum clock skew. Post-placement buffer reoptimization balances clock buffer trees to minimize clock skew and speeds up critical path delays to minimize chip timing. Initial results show upto a 55% reduction in critical path timing with only a 5% increase in area.>