Logic cell design for on-line testable FPGAs
Parag K. Lala, A.P. Singh · AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) · 2003
This paper proposes a self-checking logic cell that can be used as the building block for on-line testable FPGAs. The proposed cell consists of three 4-to-1 multiplexers, a 2-to-1 multiplexers and a D flip-flop. These multiplexers and the D flip-flop are designed using differential cascode voltage switch logic. Any single transistor fault (stuck-on/off) as well as single stuck-at faults at the inputs of the multiplexers or the D flip-flop can be detected on-line.