Multiplexed systolic shared registers
Francisco Javier Mesa-Martinez, Kaushik Narayanun, Richard Hughey · 2004
Summary form only given, as follows. The UCSC Kestrel parallel processor is a high performance SIMD computer implemented using a linear systolic array. In our current system systolic shared registers (SSR's) are used to combine computation and communication in one dimension. Our research efforts are focused on a single-chip VLSI implementation of our current 1024 processing element board. In order to address some of the shortcomings of very large SIMD array processors, our new architecture abandons the linear array configuration in favor of a 2-dimensional mesh structure. To support the added communication requirements, we have augmented our current inter-processor communication fabric with the introduction of the multiplexed systolic shared register (MSSR) architecture. We present some of the design and evaluation methods developed in order to fully understand the impact of the concepts behind MSSR. Multiplexed systolic shared registers offer greater flexibility with a minimum overhead in hardware resources. This allows our new architecture to be targeted towards applications for which our previous linear array was ill suited, at the same time that we are able to retain our original algorithmic domain. Programmability and data bandwidth are both vastly increased, thus MDSSR's can be used to generate scalable regular topologies that can be used in stream-oriented communication machines. We believe MSSR is a simple and elegant solution that will help in the implementation of very large SIMD machines in the near future.