A 32-bit microprocessor with efficient testable designs, the TX2
Y. Nozuyama, H Mitani, T. Fukumoto, Teruo Utsumi, K. Hashimoto · 2002
A 32-bit microprocessor, the TX2, with efficient testable designs, has been developed. For manufacturing test, a combination of powerful BISTs and parallel scan design is implemented. The BISTs achieve 100% functional coverage for ROM, RAM and PLA and 78% coverage of single stuck-at faults of the remaining part of the TX2 including redundant faults. Scan test vectors obtained by ATPG have enhanced the coverage to 84%. Total test time is less than 2 seconds. There are also a few circuits for efficient design verification. Moreover, for higher test quality, Idd.q test is implemented. Total area overhead is 6.9%.>