Processor implementations using queues
M.K. Milligan, Harvey G. Cragon · IEEE Micro · 1995
For several decades, designers have used queues to resolve two processor-memory interface problems - long latency and low bandwidth. Here, we discuss the evolution of instruction and branch target queues. We also explore their use to support variable-length instructions and reduce misalignment problems. From the 1956 IBM 7030 (Stretch) to today's PowerPC, we present queue configurations and prefetch strategies along with the design decisions that led to their final architectures.>