An experimental study of testing techniques for bridging faults in CMOS ICs
M. Lanzoni, Michele Favalli, M. Ambanelli, Piero Olivo, B. Riccò · IEEE Journal of Solid-State Circuits · 1993
An experimental analysis of discrete Fourier transform (DFT) techniques used to detect the presence of faulty resistive paths throughout CMOS ICs is presented. Current monitoring, delay fault testing, and new design-for-testability (DFT) techniques are compared by means of a chip designed ad hoc that allows the presence of resistive bridgings within standard functional blocks to be simulated via hardware. The results suggest that specific DFT techniques offer considerable advantages over more conventional approaches.>