On-chip hardware accelerator for model-based 3-D instrumentation using run-length matching
Masahiro Kamoshida, Takahiro Hanyu, Michitaka Kameyama · 2002
This paper presents a hardware accelerator for the high-speed model-based 3-D instrumentation whose operations are primarily occupied by the matching between an input and a projected model image. Since each 3-D reference model is represented by polygons, memory capacity for the storage of models is greatly reduced. Moreover, a new matching scheme using a run-length encoding is introduced for precise data representation with smaller memory capacity. In the hardware implementation, run-length matching is simply performed by magnitude comparisons and subtractions, it is suitable for VLSI implementation. In the proposed accelerator for high-speed run-length matching, the matching operation is performed in parallel line by line, while one-line run-length matching is performed serially. The architecture using bit-serial processing elements (PEs) can achieve ideal parallelism of run-length matching with less hardware overhead than that using bit-parallel PEs. It is demonstrated that the processing speed of the proposed hardware is about 12 times faster than that of the corresponding hardware using bit-parallel PEs.