ReBit: A Tool to Manage and Analyse FPGA-Based Reconfigurable Systems
Marco Domenico Santambrogio, Andrea Cazzaniga, Alessandra Bonetto, Donatella Sciuto · 2011
Partial dynamic reconfiguration of FPGAs is a methodology that allows the efficient use of FPGAs resources and an improved degree of flexibility with respect to static hardware when designing an architecture on FPGA. Recently several tools, aiming at supporting the designer in the implementation and the validation processes involved in partial reconfiguration, have been released. Within this scenario we introduce a framework, called ReBit, intended to be complementary to the most important of tool suite available today, e.g. Xilinx ISE suite, improving the existing features and adding new ones, such as partial bit stream scheduling policy testing and algorithmic bus macros placement, using different APIs, integrated in the framework. These features have been validated using different Xilinx FPGAs Spartan 3, Virtex II Pro andVirtex 4.