Alleviating DFT cost using testability driven HLS
Mane-Lise Flottes, R. Pires, Bruno Rouzeyre · 2002
This paper presents a method to carry out the register allocation phase of high level synthesis with testability considerations. Testability problems are identified and eliminated during this step turning testability/area trade-off to account. It allows one to decrease the cost related to the application of low-level DFT techniques.