BIST testability enhancement of system-level circuits: experience with an industrial design
Kowen Lai, C. Papachristou · 2002
A systematic methodology for testability analysis and enhancement of sequential circuit designs using Built-In Self-Test (BIST) is described. Inter-modular test insertions is applied to improve controllability as well as observability in a system level circuit. Circuit partitioning based on functionality has been applied to reduce the computation complexity. This methodology has been successfully applied to test system level circuits consisting of sequential circuit modules to do post-design re-synthesis improving overall testability. This methodology has achieved 99% fault coverage level for several different types of system level circuits from industry.