Using mission logic for embedded testing
Rainer G. Dorsch, H.-J. Wunderlich · 2001
Testing logic cores of a system-on-a-chip causes a high test data volume which has to be stored on the external au-tomatic test equipement (ATE), a high bandwidth require-ment between ATE and the chip under test implying the need for high-speed ATE. This paper reduces these requirements by reusing embedded cores during test mode as embedded testers. Hard, firm, and soft cores may be reused, since only the functionality of the core in system mode is used. The ITRS roadmap [3] predicts an increasing need for embedded testing since external testers become prohibitive expensive and the resolution of external testers relative to the chip frequency decreases. This may be avoided using embedded testers which move part of the test functionality from the ATE to the chip under test. To limit the costs for