An efficient hardware-based fault diagnosis scheme for AES: performances and cost
Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri · Virtual Community of Pathological Anatomy (University of Castilla La Mancha) · 2004
Since standardization in 2001, the Advanced Encryption Standard has been the subject of many research efforts, aimed at developing effcient hardware implementations with reduced area and latency. So far, reliability has not been considered a primary objective. Recently, several error detecting schemes have been proposed in order to provide some defense against hardware faults in AES. The benefits of such schemes are twofold: avoiding wrong outputs when benign hardware faults occur, and preventing the collection of information about the secret key through malicious injection of faults. In this paper, we present a complete scheme for parity-based fault detection in a hardware implementation of the Advanced Encryption Standard which includes a key schedule unit. We also provide a preliminary evaluation of the hardware and latency overhead of the proposed scheme.