Defects, fault coverage, yield and cost, in board manufacturing
M.M.V. Tegethoff, T.W. Chen · 2002
An analysis of the main contributors to the quality and cost of complex board manufacturing is presented. Manufacturing data from three boards built at Hewlett-Packard and simulation models are used to derive the sensitivity of quality and cost versus Surface Mount Technology (SMT) solder defect rate component functional defect rate and test coverage. A new yield model which accounts for the clustering of solder defects is introduced and a first order estimation of the cost of implementing the IEEE 1149.1 standard on ASICs is given.