Interface techniques for embedding custom mega cells in a gate array
L. Ashby · 2002
A full custom microprocessor mega cell is embedded in a 0.7-micron triple-layer metal gate array using shrinkable design rules. Interface logic built from gate array macros guarantees data sheet timing at the pins, production test pattern transportability, and CRC/BIST (cyclic redundancy check/built-in self-test) testability. The processor was modeled using behavioral Verilog wrapped around proprietary 'C' code.