A BIST scheme for on-chip ADC and DAC testing
Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Tim Cheng · 2000
In this paper, we present a BIST scheme for testing onchip AD and DA converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measuring the DNL and INL of the converters. We validate the scheme with software simulation—5 % LSB (least significant bit) test accuracy can be achieved in the presence of reasonable analog imperfection. 1