Power and performance aware reconfigurable cache for CMPs
Kamil Kędzierski, Francisco Javier Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero · 2010
This paper investigates the problem of partitioning a shared cache among threads executing in a Chip Multi-Processor (CMP). We propose Reconfigurable Cache for CMPs (ReCaC), a low-overhead run-time mechanism that dynamically partitions the cache based on the phase behavior of threads. Unlike the previously proposed performance aware partitioning approaches, ReCaC targets to use a minimum number of ways to trade-off between power and performance. ReCaC dynamically reverts back to a performance centric cache partitioning scheme if the power savings are not achievable.