Testing the unidimensional interconnect architecture of symmetrical SRAM-based FPGA

M. Renovell; P. Faure; P. Prinetto; Y. Zorian

doi:https://doi.org/10.1109/delta.2002.994634

Testing the unidimensional interconnect architecture of symmetrical SRAM-based FPGA

M. Renovell, P. Faure, P. Prinetto, Y. Zorian · 2003

This paper proposes a new and original solution to test the unidimensional interconnect architecture of a RAM based FPGA by exploring the specific properties of these blocks. The method to find a reduced set of configurations is proposed and the sequence of test vectors required for each configuration is given.

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