High-speed hardware architectures of the whirlpool hash function
M. McLoone, C. McIvor, Alison C. Savage · 2006
High-speed hardware architectures of the Whirlpool hash function are presented in this paper. A full look-up table (LUT) based design is shown to be the fastest method by which to implement the non-linear layer of the algorithm in terms of logic. An iterative Whirlpool architecture implemented on the Virtex X4VLX100 device runs at 4.79 Gbps, while an unrolled architecture achieves a throughput of 4.9 Gbps. This is faster than a SHA-512 design implemented on the same device and other previously reported hash function architectures.