Coarse-grained processor array implementing the multilayer neural network model
Francesco Piazza, M. Marchesi, G. Orlandi, Aurelio Uncini · 2002
A coarse-grained processor array which tries to overcome the limitations encountered when a network composed by many neurons has to be mapped into a limited number of processing elements (PEs) is proposed. Given the total number of PEs, the proposed architecture can be configured to implement any particular multilayer perceptron (MLP) topology, and can simulate both the forward and learning phases of the network. Moreover, it has a small number of very local connections, and can exhibit a high efficiency under limited constraints on the number of neurons per layer.>