Efficient state reduction methods for PLA-based sequential circuits
M.J. Avedillo, José María Quintana, J.L. Huertas · IEE Proceedings E Computers and Digital Techniques · 1992
Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are shown. The area of the PLA implemention of the combinational component and the design time are used as figures of merit. The comparison of such parameters, when the state reduction step is included in the design process and when it is not, suggests that fast state-reduction heuristics should be implemented within FSM automatic synthesis systems.