System Validation by Three-level Modeling Synthesis
K. A. Duke, H. D. Schnurmann, T. I. Wilson · IBM Journal of Research and Development · 1971
The experimental three-level system modeling technique discussed in this paper can be used during the design stage of a system for identifying mismatches among the architectural, microprogramming, and hardware logic levels. Compatible switching between modeling levels is emphasized. Execution of an application program by the architectural and microprogramming level models with switching between levels is illustrated.