The CALLAS synthesis system and its application to mechatronic ASIC design problems
P. Windirsch, P. Duzy · 2002
The authors demonstrate the use of high-level synthesis for ASIC designs in the mechatronic application domain. The first chip synthesized and fabricated is part of a distance measurement system. Only six weeks were needed for the design of the 2700 equivalent gates ASIC. The hand-crafted standard cell design had taken four times as long for a result of comparable size and performance. Similar results have been obtained in a second ASIC project, which is part of a friction clutch controller.>