Design of SoC verification platform based on VMM methodology
Lu Kong, Wuchen Wu, Yong He, Ming He, Zhonghua Zhou · 2009
A VMM-based verification platform has been implemented and applied to Yak SoC in this paper. The whole verification environment uses the SystemVerilog language, and the simulation tool adopted is Synopsys VCS-MX200606. The verification IP and SystemVerilog assertions help to heighten the performance of the platform. The verification results indicate that design errors of timing and anti-protocols have been exactly checked out with 100% verification coverage. The proposed platform, possessing fine configurability, flexibility and high performance, can be reused in similar verifications of other design.