Effective concurrent test for a parallel-input multiplier using modulo 3
Warren H. Debany, Anthony R. Macera, D.E. Daskiewich, M.J. Gorniak, Kevin A. Kwiat, Heather B. Dussault · 2003
Experiments were performed to determine the effectiveness of modulo 3 checking for a class of two's complement, parallel-input multipliers. A full gate-level simulation of stuck-at faults was performed. The probability of aliasing for a 12*12-bit multiplier was found to be only 5.196%. The assumption that bit errors are statistically-independent yields a much greater probability of aliasing.>