A new linear systolic array for FFT computation
J. Choi, Valentin Boriakoff · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 1992
The authors propose a linear systolic array for fast Fourier transform (FFT) computation that is based on the Pease algorithm, which has the advantage of making the systolic array structure uniform from stage to stage. With slight modifications the algorithm can be directly implemented on a systolic array. The array needs only log/sub 2/n processors, where n is the number of input words (length of the FFT). It processes data generated at a speed twice the rate of the processor clock.>