Semi-systolic bit level arrays for high speed convolution
Elcherif, Samia A. Mashali, El-Sherif · 1989
A bit-level array is presented for high-speed convolution. With much less hardware complexity, the proposed array provides speed which is equivalent to that of a fully pipelined systolic array for convolution. It is shown that enormous hardware savings can be obtained when the systolic convolution algorithm is reformulated in terms of the most basic vector reduction operation, namely multioperand addition.>