On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard
M. Aberbour, Alain Houelle, Habib Mehrez, N. Vaucher, Alain Guyot · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1998
In this paper, we investigate the design of macrocell generators of division and square root floating-point operators. The number representation used in our operators is the IEEE-754-1985 standard for binary floating-point numbers. The design and implementation of the generators rely on a powerful multi-view macroblock generator tool called GenOptim. This computer-aided design (CAD) tool is able to output a set of different descriptions for several VLSI technologies as well as field programmable gate arrays (FPGAs). The division and square root operators described in this paper use the signed-binary-digit representation. We start first by describing the operators for the significand, then we investigate the IEEE floating-point operators. Throughout this paper, and wherever appropriate, we present the implementation results using the GenOptim environment.