A method for testability analysis and BIST insertion at the RTL
Joan E. Carletta, C. Papachristou · 1995
The goal of this research is to provide a means for BIST and circular BIST analysis and evaluation at the register transfer level (RTL). RTL circuits consist of interconnections of registers, functional units (ALUs), multiplexers and buses. The analysis is done via two metrics that measure the e ectiveness with which an individual register in the circuit generates test patterns, the entropy-based randomness [1] and expected state coverage. The testability metrics are computed by means of a Markov chain model that takes as input the RTL circuit description, and provides analytical values for the probability distribution of the state of each register in the circuit. The Markov model works by partitioning the circuit into small pieces, each containing the information necessary to analyze a single register. It then models each register separately as the register moves from state to state. A wide variety of BIST methodologies, including conventional, MISR-based, and circular BIST, can be modeled with this technique. The motivation for this work lies in BIST insertion, which requires the selection of test registers. Traditionally, each ALU in a circuit is made directly testable by placing controllable registers (TPGRs) at the ALU's inputs, and observable registers (MISRs) at the ALU's output. However, this addition of test registers may not be necessary. For example, suppose that the input registers to the ALU are not directly controllable, but that they still generate patterns that are random enough to e ectively test the ALU; in this case, there is no need to replace the registers with more expensive test pattern generation registers. Thus, in selecting test registers, a tradeo between cost and test e ectiveness can be made; using fewer test registers will save hardware and have a less negative impact on system performance, but may haveanadverse ef-