A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion
Irith Pomeranz, Zvi Kohavi · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1992
The authors describe a method for increasing the testability of digital circuits for single line stuck-at faults at the logic gate level by the addition of controllable and observable points in structures called testing modules. They also present a test generation algorithm that generates complete test sets, i.e. test sets that cover every possible fault, for increasingly large subcircuits. The test generation algorithm forms the basis for the design-for-testability method described. The authors introduce the concept of exhaustive test generation and of test set reduction, and show that the worst-case complexity of test generation can be estimated on the basis of the these concepts, without having to perform worst-case test generation. They describe the testing-module placement algorithm, whose aim is to reduce the complexity of test generation. It is based on the estimated complexity of test generation as developed. The extension of the method to sequential machines is briefly discussed.>