Conversion of a CMOS logic circuit design to an RSFQ design considering latching function of RSFQ logic gates
Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi · IEEE Transactions on Applied Superconductivity · 2014
A method for converting a CMOS logic circuit design to an efficient RSFQ design, which minimizes the number of flip-flops during conversion, is proposed. In an RSFQ circuit, each data input terminal of a logic gate has latching function, and the function is enabled or disabled depending on the order of the arrivals of the data pulse and the corresponding clock pulse. The number of flip-flops is minimized by the use of the latching functions through arrangement of the order of pulse arrivals of each gate and also by circuit retiming. A conversion tool based on the proposed method has been developed. Conversion results of CMOS benchmark circuits show that most of the flip-flops in the circuits are eliminated by the proposed method. A 4-bit RSFQ processor was successfully designed by an existing CMOS design tool and the developed conversion tool.