Image processor capable of block-noise-free JPEG2000 compression with 30 frames/s for digital camera applications
Hideki Yamauchi, Shigeyuki Okada, K. Taketa, Tatsushi Ohyama, Yuh Matsuda, Tsugio Mori, Shinichiro Okada, Tsuyoshi Watanabe, Yoshihiro Matsuo, Yuji Yamada, Tatsuya Ichikawa, Yoshifumi Matsushita · 2003
A one-chip image processor for next-generation digital cameras and broadband PDA multimedia mobile phones is described. It is capable of processing JPEG2000 data with 30 frames/s and a 27 MHz operating frequency. The process is fabricated in 0.25 /spl mu/m CMOS and contains 8.5M transistors in a 103 mm/sup 2/ area.