A New Variable Testability Measure: a Concept for Data-Flow Testability Evaluation
M. Jamoussi, B. Kaminaka, Dinkar Mukhedkar · 2005
In this paper, we propose a new Variable Testability Measure (VTM) applied at the high-level synthesis stage of the circuit- design process. The proposed approach is based on Binary Decision Diagrams representing fully fhnctional blocks of a circuit, and on their Cyclomatic Testability Measures. This new measure aims the evaluation of hnctional-primitive testability appropriate for data flow level. I. INTRODUCTION In recent years, the use of silicon compilation and other standard cell-design tools have changed the way digital systems are designed. As a result, more and more systems are being designed at the func- tional level, with little gate-level design being explicitly performed. Instead of creating a system with gates, designers are using func- tional modules such as adders, multipliers, etc. By understanding that designs are constructed using functional-level components, an appropriate measure can be developed which efficiently represents knowledge about functional-level testability. This paper addresses an approach for implementing testability in the high-level synthesis process and particularly at the functional- level stage of the synthesis. A new Variable Testability Measure (VTM) is defined and used in the data-flow level. In section II, high- level synthesis is revised and briefly we review certain works related to implementing the testability of integrated circuits in their design process. In section III, a new approach'for testability at the functional level, called Variable Testability Measure (VTM) is introduced The use of the proposed measure and experimental results are presented in sections IV and V.