Compiler Assisted Dynamic Management of Registers for Network Processors
Ryan Collins, Fernando Alegre, Xiaotong Zhuang, Santosh Pande · SMARTech Repository (Georgia Institute of Technology) · 2005
Modern network processors support high levels of parallelism in packet processing by supporting multi-ple threads that execute on a micro-engine. Threads switch context upon encountering long latency mem-ory accesses and this way the parallelism and memory access can be overlapped. Context switches in the typi-cal network processor architectures such as the IXP are designed to be very fast. However, the low overhead is partly achieved by leaving register management to pro-grams, with minimal support from the hardware. The complexity of the multi-engine, multi-threaded environ-ment makes manual register management a daunting task, which is better left to a compiler. However, a purely static analysis is unable to achieve full utiliza-tion of the register file due to conservative estimates of liveness. A register that is live across a context switch point must be considered live for the duration of all other threads, and so it must be assumed to be unavailable to other threads. In addition, aliasing fur-ther reduces the effectiveness of static analysis. The net effect is a large number of idle cycles that are still present after static optimization. We propose a dynamic solution that requires mini-mal software and hardware support. On the software side, we take a pre-allocated binary file and annotate the potential context switch instructions with informa-tion about the dead registers. On the hardware side, we try to rename the transfer registers and addresses to dead general purpose registers and update the usage of registers. We then replace the long-latency memory instructions with fast move instructions in the archi-tecture using the dynamic context. The results show up to 51 % reduction in idle cycles and up to 14 % increase in the throughput for hand coded applications on Intel IXP 1200 network processor. 1