A design scheme for PLA-based control tables with reduced area and time-delay cost
C. Papachristou, A.L. Pandya · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1990
A novel programmable logic array (PLA) design that is very effective when it applies to control tables, i.e. structured tables representing functions of control nature, is presented. The PLA synthesis of control tables is achieved by the techniques of partition and fusion under area and time-delay design constraints. The partition technique exploits the data sparsity by splitting the control table along its columns into several smaller parts using heuristic breadth-first directed graph search. The fusion process takes advantage of the data multiplicity by sharing common symbolic PLA fields into distinct fields using a new encoding scheme. The partition process is performed only on the OR array of the symbolic PLA, whereas the fusion process performs the mutually exclusive encoding in the AND arrays of the partitioned PLA parts. A final channel routing of the PLA parts is also provided to reduce the routing area overhead required. The PLA synthesis of control tables scheme has been implemented in C and runs in Unix on VAX, Apollo, and Sun machines. An experiment using randomly generated data tables was very encouraging, particularly for large PLAs having a sparse and multiple personalization.>