Design validation: comparing theoretical and empirical results of design error modeling
Sungho Kang, Stephen A. Szygenda · IEEE Design & Test of Computers · 1994
To use simulation for design verification, designers need a confidence measure for a given set of simulation patterns, specifically for cases in which only a subset of the possible patterns is used. The authors derive a measure of design verification coverage based on the number of design errors detected in a theoretical analysis of a circuit. To verify the theoretical analysis, they simulate errors and compare the results.>